Generate DDR5 AMI models with Sigrity SystemSI

Over the past few years, many system designers have been using DDR4 RAM components for system design. As product performance continues to increase and power budgets continue to decrease, expectations for faster memory devices never stop. In 2013 , even though DDR4 has been widely used in mainstream design, the DDR5 standard is still in the specification stage. Although the final version of the DDR5 specification has not been promoted in the industry, the main features of DDR5 are well known: DDR5 will provide twice the bandwidth of DDR4 RAM and more efficient power management.

As the market is waiting for the official use of DDR5 devices, it is likely that in late 2018 , system designers will feel more anxious about the DDR5 specification. They want to know how much it will cost to upgrade system requirements in order to support new RAM performance, take advantage of increased data rates and power consumption levels. Therefore, they hope to start prototype design based on known DDR5 characteristics as soon as possible , and then study the use of DDR5 bus system in specific products .

For experienced designers, using a new memory interface to build a prototype means first collecting a device model that represents the behavior of the interface, and then using the new model to validate and simulate new features using the simulation tool or environment through the DDR5 specification. Unfortunately, for almost all designers, the schedule is stagnant here because there is no device model for DDR5 RAM .

One might say that a memory device is a simple receiver during the write cycle and can be represented by any existing IBIS receiver model. This was possible 15 years ago. However, today's things are not so simple. For engineers who have been designing systems with higher speed DDR4 RAM such as 3200Mbps , the reason is obvious. High data rate memories use serial link filtering techniques such as equalization to ensure signal quality. These filtering methods are modeled only by the IBIS-AMI model and are provided by the memory and controller manufacturer. Since DDR5 will have faster speeds and even lower voltage swings, equalization is more important. Therefore, system designers should use advanced models of controllers and memory to emulate new DDR5 interfaces. At this point, the designer cannot get any models from the manufacturer.

Now, we can all feel the pain of the designers: on the one hand, they are eager to build a system, and they hope to cooperate with the main functions of DDR5 RAM ; on the other hand, they lack models suitable for this kind of experiment; what makes them frustrated is that these The model may not be available for the time being. The biggest worry for design engineers is that if competitors get the model first, take advantage of DDR5 to release the product earlier. The hard part doesn't stop there: even if the model is available, designers still don't know if their current simulation tools can support the simulation capabilities required for DDR5's new data transfer features.

As a tool provider, one of the main goals should be to help design engineers get out of model dependencies and provide choices so they can create their own models for emerging interfaces / technologies. Can this be achieved?

For Sigrity users, the answer is YES . In fact, for engineers using Sigrity SystemSI 2017 , the solution is already in their hands! It was a surprise, but it is a fact!

Sigrity SystemSI has a built-in IBIS-AMI model generator: AMIBuilder . This embedded tool uses the SystemSI GUI to accept user-defined AMI model parameters and create AMI models with user-required or default IBSIS/O buffer models. Our users, including our Cadence IP team, have been using this tool to create DDR4 models. Recently, some of them have used the FFE / DFE technology to generate the DDR5 AMI model and successfully completed the test system design and predicted DDR5 behavior. This of course also makes many designers worried about another problem: Even with DDR5 AMI model, my simulation tools are also bus DDR5 DDR5 support functions required? SystemSI is equipped with a power- saving solution that uses Cadence 's patented channel emulation technology for bus characterization and simulation.

So, for anxious design engineers and SI engineers, there is no need to wait for the final specification of DDR5 , or wait for controllers and memory manufacturers to provide DDR5 models; Sigrity SystemSI can help you create prototypes and help you understand how DDR5 is in your Work in the app. So don't worry!