The merger of designs can be tricky. Usually when you need to solve a problem, the change will affect other parts of the design, and other problems will inevitably arise. In 2017.3 we introduced a new feature that can help you solve this problem. This feature is called configurable reporting.
The configurable report is a new Vivado project feature that allows you to run any report at any step of the process. For example, suppose you have a critical path after implementation, and you are not sure how to solve it. To understand how this critical path "evolved" between processes, configurable reports allow you to report the timing of that exact path at the completion of logic optimization, layout design, layout design, and any steps between them. Figure 1 shows the report timing summary that was added to each of the fulfillment process steps. Understanding the timing of each step can help you understand whether the problem is a synthesis issue, a utilization issue, a clock distribution issue, or a cabling congestion issue.
Figure 1. Configure the time series statistics report in the running implementation properties tab to be generated after the completion of the three process runs
Based on the description of configurable reports above, we will introduce the concept of reporting strategies. Similar to running strategies that allow you to adjust Vivado's performance to meet your unique needs, reporting strategies allow you to tailor reports to your design. You can configure report policies and reuse them across different runs and even different projects. We provide several pre-configured policies, including: UltraFast method reports, performance discovery reports, timing closure reports, or if you just want to run faster, you can choose the no reports option. Figure 2 shows the tool settings window where users can create their own custom policies or view Xilinx's recommended policies. Figure 3 shows the Design Run window, which contains a number of implementation and synthesis runs configured with different run and report strategies.
Figure 2. Tool settings window, allowing users to create their own custom strategies
Figure 3. The Design Run window shows several run and report strategies
Configurable reports give you the flexibility to decide which reports are most critical to your design and enable you to focus on solving your unique problems. When you finally promote and end your design, the only problem you will encounter is to open a cork stopper that celebrates your bottle! "Hey!" Bingo!
About the author Brian Lay is a senior product marketing manager for the Vivado IDE and supporting infrastructure. As an IDE marketing manager, he has participated in many different Xilinx projects, including timing constraint wizards, partially reconfigured project support, and run-time hardware debugging. Brian holds a master's degree in electrical engineering from the University of Illinois at Urbana-Champaign and a bachelor's degree from the University of Minnesota. He has worked at Sun Microsystems and Advanced Micro Devices and has more than 17 years of experience. His skills include full custom circuit design, integrated layout and routing, clock distribution design, full-chip integration and timing, noise, power, DRC, IR drop in all aspects to verify these circuits in the CPU, GPU and FPGA.
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