Designing asynchronous binary subtraction counters with JK flip-flops

CM51932768DZFT-K

The counter can be divided into synchronous counters and asynchronous counters according to the input mode of the counting pulses. Synchronous counter: the implementation is to introduce the counting pulse to the CP end of all the flip-flops, so that the flip-flops can be flipped at the same time; the asynchronous counter: the implementation does not lead the counting pulse to the CP end of all the flip-flops, but Leading the output of the other flip-flops to the CP side of the other flip-flops does not occur at the same time.