The following figure is the circuit diagram of the +3.3V power supply of the LogIC235 power supply (the circuit is not shown in the figure). It is powered from +5V, regulated by the FET SSP35N03 and then passed through L1, L2, C1, C2. Filtered output +3.3V power supply. The voltage regulator circuit is sampled from the +3.3V output terminal by R1, R2, and R3, and sent to the 7th pin of the comparator LM339, and the 6 pin is sampled from +5VSB, and the stable voltage obtained by dividing the R4 and R5 is compared. After that, the error voltage is sent from the 1 pin to the inverting terminal 10. In addition, the sawtooth wave oscillation signal of pin 5 of TL494 is sent to the 11th pin of LM339 through the 10kΩ resistor. Compared with the voltage of pin 4 of LM339, the sawtooth signal is only the part larger than the voltage of pin 10 to get the 13th pin of LM339. The pulse signal is output and amplified by a triode to push Ql. If the voltage of +3.3V rises for some reason, the voltage of the output of the 1 pin is also the voltage of the 10th pin of the LM339, so that the pulse width of the output of the 13 pin is narrowed, and the voltage of the output of Q1 falls back, which acts as a voltage regulator. The role. To adjust the output voltage, a parallel resistor on R3 can increase the output voltage, and a parallel resistor on R2 can reduce the output voltage.
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