1. Status register STATUS 
2. Indirect addressing registers INDF and FSR
3. Register PCL and PCLATH related to the program counter PC
4. Power Control Register PCON 
PIC microcontroller instruction system
The PIC16F87X has a total of 35 instructions, each of which is a 14-bit single-byte instruction. All instructions are divided into three categories according to the operation object: byte-oriented operation class (17); bit-oriented operation class (4); constant operation and control operation class (14).
PIC configuration word settings
I have learned two ways to configure the PIC configuration word so far:
1. Two "_"s are followed by CONFIG, followed by the value after the configuration word is set;
2. The two "_"s follow CONFIG, followed by the bits and status of each configuration word. The format is as follows:
;========================================================== =================
; configuration word definition
;========================================================== =================
__CONFIG _DEBUG_OFF&_CP_ALL&_CPD_ON&_LVP_OFF&_BODEN_OFF&_PWRTE_ON&_WDT_OFF&_HS_OSC ; Configuration Word Definition Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register and addressing the INDF register will result in indirect addressing.
Indirect addressing is achieved using the INDF register. The instructions to any INDF register actually access the registers pointed to by the pointer register FSR. Indirect reading of the INDF register itself returns 00H. Using an indirect addressing to write to the IDNF register will result in a dummy operation (although it may affect the status bits). A valid 9-bit address is obtained by combining the 8-bit FSR register with the IRP bit (STATUS). An example is as follows:
Example of indirect addressing:
Example: Write 30H~7FH to 30H~7FH units in turn. Where COUNT is the count register.
;========================================================== ================
; Continuous address write data subroutine (indirect addressing)
;========================================================== ================
WR_ADS: MOVLW 30H; the following initializes the RAM contents
MOVWF FSR; starting from 30H unit
MOVLW 30H; assign the value 30H to unit 30H
MOVWF COUNT ;
INTRAM: MOVF COUNT, 0 ; assign 30H to 7FH to units 30H to 7FH
MOVWF INDF ; operates on INDF
INCF COUNT,1 ;COUNT+1
INCF FSR, 1 ; pointer +1
BTFSS COUNT,7 ;COUNT is 1 (COUNT=0 at 7FH)
GOTO INTRAM ;
RETURN ; program returns
The PIC microcontroller register is defined in the PIC microcontroller programming, you need to define the registers you need in the program. Generally, pseudo instructions are used. But using the following method can be easier.
Use CBLOCK followed by the address of the register to be defined. It can be defined by multiple registers together, and the register address will be automatically assigned to the next address. Use ENDC to complete the definition when you finish defining it.
An example is as follows:
;========================================================== ================
; space definition
;========================================================== ================
CBLOCK 20H; defined from 20H
COUNT ; address is 20H
W_TEMP; address is 21H
STATUS_W; address is 22H
ENDC; end definition
The operation of the PIC microcontroller I/O sets a position in the TRISX register to the corresponding output driver in the high-impedance mode. Clearing a bit in the TRISX register will latch the contents of the output latch to the specified pin.
RCSTA Register Operation Precautions In the process of receiving data, if the received data is read out in time, the USART will normally receive the data sent next time. However, if an interrupt occurs during reception, or other interrupted operation is interrupted, the data in the RCREG is delayed in time. At this point, the shift register will no longer put any data into the RCREG. In this case, even if there is data transmission, the RCIF flag will not be set and the reception will be interrupted. If no action is taken, the communication will be completely interrupted.
The cause of this problem is that the above operation interrupts the reception and delays the data fetching in time, causing the overflow flag OERR (RCSTA) in the RCSTA register to be set. This flag bit disables the shift register from placing the received data in the RCREG and cannot continue to receive.
The solution to this problem is to clear OERR. Clearing OERR does not directly operate on this flag. The overflow error flag OERR must be cleared by clearing the enable continuous receive bit, CREN (RCSTA). However, after clearing the continuous receive bit CREN (RCSTA), the bit must be set again. Otherwise, only one byte can be received.
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